In conventional design of a semiconductor integrated circuit, the operation of a combined circuit of registers (flip-flops) has been described in a hardware description language such as RTL (Register Transfer Level). Since the circuit scale of an integrated circuit has been increased in recent years, design using a hardware description language requires much design time. Accordingly, there is a proposed technique for making design using a high-level language such as the C language, the C++ language, the SystemC language, or the Matlab language, which has higher abstraction than a hardware description language and then automatically generating RTL. The tools for achieving this are commercially available as high level synthesis tools.
The designer can make circuit design by inputting a source code described in a high-level language and a circuit specification to a high-level synthesis tool. In addition, the designer inputs circuit specifications that cannot be represented by a high-level language or cannot be represented efficiently by a source code to a high level synthesis tool by setting high level synthesis options such as an option, attribute, and pragma.
These high level synthesis options have effects on the latency, the area, the throughput, the power consumption, the amount of memory use, the amount of multiplier use, and the like, which are the non-functional requirements of a circuit. A high level synthesis tool has high level synthesis options for specifying conversion of arrays to memories or registers or for specifying pipelined computation or non-pipelined computation. By setting these high level synthesis options without changing the operational description of a source code when high level synthesis is performed, the amount of memory use and throughput, which are non-functional requirements, can be obtained easily.
That is, a desired circuit can be obtained by trying to combine these high level synthesis options and selecting the optimum circuit that meets the characteristics (that is, non-functional requirements) obtained from the try results.
However, since there are enormous combinations of these high level synthesis options, the speed of a search needs to be enhanced. PTL 1 discloses the method for enhancing the speed of a search in the design space of the high level synthesis options by defining the design space.